ASIC Physical Design Engineer - Acacia

Job Description

Acacia, now part of Cisco, develops leading edge transceiver hardware for optical communication over fiber lengths from 100km to greater than 10,000km, at bandwidths from 100G to 1.2Tbps. This requires complex DSP algorithms in addition to novel low-power semiconductor development techniques. We package the latest CMOS node ASICs along with millimeter-wave analog and silicon photonics devices in order to provide the smallest form factor, highest bandwidth and lowest power products on the market. We are looking for a ASIC Physical Design Engineer who will be a member of a team working on next generation 100G-1T coherent optical communications products. This role is a senior contributor focused on delivering highly-complex ASICs in advanced technology nodes that are used in these next-generatio n telecom systems. The role involves detailed physical guidance of floorplanning, placement and routing to produce high quality design, including the responsibility of delivering tape-out quality across all the analysis checks, in a highly team focused environment
Key Essential Functions
* Deliver on physical design implementation activities such as driving the following across all major EDA tool suites: power analysis, electromigrati on, IR signoff process corner decisions, floor planning & partitioning, synthesis, place & route, static timing analysis (STA), formal equivalence check, Clock Tree Synthesis, timing closure, signal integrity, power grid analysis, physical verification DRC/LVS
* Work closely with RTL designers to debug and root-cause Physical Implementation issues related to design, tools, etc. and arrive at a feasible solution through the augmentation of input and design collateral.
* Deliver design flows for place & route, STA, formal equivalency, power grid analysis or physical verification DRC/LVS across the design space. Manage stakeholders across analog and digital teams while interfacing with EDA vendors on issues/feature s /enhancements.
Other Duties
* Perform other duties as assigned
Minimum Q ualifications, Experience, Skills, Education and Certifications
* Bachelor’s Degree in electronic engineering, or the equivalent qualification in training and experience
* At least 8 years of professional engineering experience, including experience in advanced technology nodes: 5nm and below
* Familiar with industry standard CAD methodologies from Cadence, Synopsys and/or Mentor
* Good scripting skills with Perl and TCL
* Successful execution of ASICs from product definition to production release
* Solid analytical, communication and presentation skills
* Self-motivated and the ability to drive without supervision
Other Co nsiderations/Q ualifications
* Finfet expertise
* Prior experience in telecom design space
* Experience with digital signal processing algorithms is a plus
* Exceptional written & verbal communication skills
Special Physical/Trave l Requirements
* None
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.
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