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Staff CAD Engineer - Remote

Silicon Labs

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Job Details

Location: Austin, Travis County, Texas, USA Boston, Suffolk County, Massachusetts, USA Beaverton, Washington County, Oregon, USA USA Seattle, King County, Washington, USA Posted: Feb 26, 2021

Job Description

Who We Are

We are Silicon Labs. We are the leading provider of silicon, software, and solutions for a smarter, more connected world.We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem, and robust support make us the ideal long-term partner in building advanced industrial, commercial, home, and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives. silabs.com

Job summary

As a senior member of our CAD team, you will develop, maintain, enhance and debug Process Design Kits (PDKs) and layout flows for our rapidly growing IoT, Timing, and Power product divisions. This is a high visibility role, which requires fluid interaction with Silicon Labs’ foundry, CAD, ESD, Design, Packaging, and Layout teams. The candidate should have excellent grasp of PDK development, SKILL programming, Cadence Virtuoso IC61 and 18.xx tools, Techfile development, netlisting development for LVS and Simulation, Place and Route requirements (LEF/DEF files). Proven experience working across a range of process nodes from smaller geometries (22nm and below) to high voltage processes (0.5u) is critical for the role.

Education and Experience

  • 8+ years of experience in PDK and SKILL code development, preferably writing from scratch and/or modifying existing pcells and netlistcode
  • Experience with Cadence Virtuoso Layout tools and their customizations
  • Proven programming skills in SKILL, Perl, Python, Tcl and Shell scripting
  • Good debug experience reviewing Calibre LVS and DRC errors
  • Knowledge of Calibre RVE, DRV and Cadence QRC would be useful
  • Familiarity with Analog and Digital design engineering concepts
  • Excellent documentation and communication skills. Familiarity with Jira and Confluence is considered a plus
  • Familiarity with leading version control tools like Perforce, Cliosoft, Methodics are considered a plus
  • Open to candidate working 100% remote in AZ, CA, IL, TN, FL, GA, MI, MN, NH, UT, VA, OR

Benefits

  • Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental & vision plans
  • Highly competitive salary
  • 401k plan with match and Roth plan option
  • Equity rewards (RSUs)
  • Employee Stock Purchase Plan (ESPP)
  • Life/AD&D and disability coverage
  • Flexible spending accounts
  • Adoption assistance
  • Back-Up childcare
  • Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)
  • Flexible vacation policy
  • 3 paid volunteer days per year
  • Charitable contribution match
  • Tuition reimbursement
  • Free downtown parking (Austin)
  • Onsite gym (Austin)
  • Monthly wellness offerings
  • Free snacks
  • Monthly company updates with our CEO

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
Design Automation ; EDA ;

About Silicon Labs

A worldwide fabless semiconductor company headquartered in Austin, Texas, United States. Silicon Labs provides silicon, software and devices for the Internet of Things, Internet infrastructure, industrial automation, consumer and automotive markets.

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