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Chip Packaging Reliability Technologist

Google

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Job Details

Location: Sunnyvale, Santa Clara County, California, USA Posted: Feb 19, 2020

Job Description

Qualifications

Minimum qualifications:

  • 5 years of experience in chip packaging reliability and failure analysis.
  • Experience in implementing test vehicles and accelerated reliability tests, setting up reliability test matrix for qualification, selecting reliability screen test methods for production, and bench testing.
  • Experience with chip packaging reliability principles and Physics-of-Failure concepts.
  • Experience in product development.

Preferred qualifications:

  • Mater's or PhD degree in Electrical Engineering, Material science, related field, or equivalent practical experience, with specialization in semiconductors.
  • Understanding of package technologies, Chip-Package-Interaction (CPI) and reliability testing for both component and board level.
  • Knowledge of statistical techniques to analyze test data and to create estimates for field failure rates.
  • Familiarity with hardware, test equipment, and vendor labs for reliability tests implementation and execution.
  • Good project management and communication skills.

About the job

As an Chip Packaging Reliability Technologist, your primary responsibility will be to develop and implement methodologies and techniques to evaluate and enhance product reliability. You will work closely with cross-functional teams to define semiconductor device and package reliability requirements for both new technology qualification and product qualification. You will lead the design of reliability test structures, reliability test plans suitable to our datacenter applications and conformance to industry standards. You will also lead failure analysis from reliability testing to closure with corrective actions using structured problem solving approaches. You will engage in reliability testing and failure analysis planning with our supply chain partners to support product and technology development.

Responsibilities

  • Manage chip packaging reliability assessment and testing. Work with new products or new technologies from the concept phase to high volume production while interfacing with cross-functional teams and external vendors/partners.
  • Perform reliability risk modeling, assessment and life predictions (Weibull analysis, Arrhenius modeling) on new product or new technology development.
  • Execute reliability tests for the qualification of various packaging technologies with advanced Si nodes to meet our datacenter system requirements.
  • Drive failure analysis for reliability and product qualification failures across design, silicon, and package and assembly domains.

Location

At Google, we don’t just accept difference—we celebrate it, we support it, and we thrive on it for the benefit of our employees, our products and our community. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing this form .

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

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