Senior Digital Simulation/Verification CAD Engineer

Job Description

We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.Responsibilities:

· Flow-development

· Work with digital design verification engineers across multiple design groups and sites to understand requirements and deliver consistent and uniform solutions throughout the organization

· Evaluate new verification tools to assess their integration into existing flows

· Define and implement improvements to existing flows to stay ahead of project needs

· Support

· Provide day-to-day support of existing digital verification methodologies

· Interface with EDA Vendors

· Ensure that their tools are properly integrated into the Silicon Labs flow

· Report any bugs and ensure their timely fix

· Documentation and Training

· Create detailed documentation for digital design verification flows at Silicon Labs

· Provide creative ways (such as Lunch and Learn, Symposium papers, etc.) to ensure that designers are kept aware of CAD-supported flows

Job Requirements:

· BS or MS in Electrical Engineering or equivalent

· 5+ years of working in or using Digital front-end simulation and verification tools and flows (e.g. Xcelium, Questa, Jasper Gold, Questa Formal)

· Strong knowledge of digital design and verification engineering fundamentals

· In-depth knowledge of Design Verification Tools (Functional and Formal), on how they work, the data they produce and the appropriate use-cases for each flow

· Strong familiarity with Verilog, System Verilog, VHDL

· Familiarity with RTL and Gate-level simulations

· Working knowledge of vendor debug tools (e.g. SimVision, Visualizer)

· Hands-on experience in scripting using PERL, Makefile, TCL and any other scripting languages

· Working knowledge of version control tools (e.g. svn, git)

· Excellent written and verbal communication skills

· Knowledge of Real Number Modeling (VerilogAMS wreal or System Verilog UDN) is a plus

· Knowledge of CortexM based systems is a plus

· Familiarity with low-power designs in multiple power domains (e.g. UPF, CPF) is a plus

· Testbench design (using System Verilog or UVM) is a plus

· Knowledge of Verification Planning and Management (e.g. Cadence vManager) is a plus

· Assertion-based verification (e.g. SVA) is a plus

· Familiarity with AMS simulations is a plus, but not required

Benefits

• Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans
• Highly competitive salary
• 401k plan with match and Roth plan option
• Equity rewards (RSUs)
• Employee Stock Purchase Plan (ESPP)
• Life/AD&D and disability coverage
• Flexible spending accounts
• Adoption assistance
• Back-Up childcare
• Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)
• Flexible PTO schedule
• 3 paid volunteer days per year
• Charitable contribution match
• Tuition reimbursement
• Free downtown parking
• Onsite gym
• Monthly wellness offerings
• Free snacks
• Monthly company updates with our CEO

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.